1. Field of the Invention
This invention relates generally to semiconductor device design and testing and, more particularly, to a method and apparatus for determining critical timing path sensitivities of macros in a semiconductor device.
2. Description of the Related Art
Integrated circuit architectures are continually evolving to improve and extend the capabilities of systems, such as computer systems powered by microprocessors. Execution speed, power consumption, and circuit size are aspects of microprocessor performance that are constantly addressed by processor architects and designers in the ongoing quest for an improved product. Execution speed not only depends on the clock rate of a processor, but also upon the speed of interfaces such as cache memories and buses that supply instructions and data for execution by a processor core. The execution speed of microprocessors is heavily analyzed and compared using various tests.
Integrated circuit devices, such as microprocessors, include a plurality of submodules (i.e., commonly referred to as macros) on a single semiconductor chip, or die, that cooperate to perform the functions of the device. Designing a microprocessor circuit typically involves modeling the functions of the macros with a software simulation and determining timing parameters for the macros. Logic races are conditions that occur in situations where logic gates are enabled by signals received from a clocked device. Problems may occur in a synchronous device if a clock edge is received too early, or if the edge is too late. The availability or stability of the data signals may not coincide with the clock edge.
During the design process of the integrated circuit, the arrangements of the macros, the performance resulting from the layout, and other design effects are difficult to anticipate. Therefore, a designer has difficulty ascertaining how aggressively to set device dimensions that determine the timing characteristics in a synchronous system. If the timing is set too aggressively, logic races may result, since logic race conditions are generally avoided by delaying clock signals with respect to data. However, if the timing is not sufficiently aggressive, the integrated circuit speed performance may be compromised.
One technique for adjusting the critical timing edges of macros within an integrated circuit is the use of self-timed pulse control (STPC) circuits to change the timing of supplied clock signals. An exemplary STPC system is described in U.S. Pat. No. 5,964,884, entitled, “Self-timed pulse control circuit,” and incorporated herein by reference in it entirety. In general an STPC circuit provides a variable amount of delay in the path traversed by the clock signal that is supplied to a macro. In one example, six alternate clock paths may be provided, with each path having a varying delay characteristic. The specific number of paths depend on the particular macro and the granularity of the control desired.
During the design of an integrated circuit, the timing relationships between the macros are typically modeled using a global interconnect analysis. Based on the interconnect analysis, the particular clock path for each macro is selected (i.e., referred to as the zero path or zero STPC setting). Paths that are faster than the zero path are said to have a negative STPC offset, and paths that are slower than the zero path are said to have a positive STPC offset. Typically, once the zero paths are selected, the default timing for the macros may not be changed without a design review. Certain integrated circuits, such as microprocessors, have dedicated test modes where various settings, including STPC settings, can be manipulated for judging the performance characteristics and stability of the device. Industry standards related to such testing modes have been promulgated by the Joint Test Access Group (JTAG) consortium. Hence, the dedicated testing mode is commonly referred to as a JTAG mode. An integrated circuit testing system is used to drive the pins of the microprocessor for changing various JTAG settings and for running test operations.
Typically, a microprocessor is placed in a JTAG mode when the tester drives a series of signals having a predetermined timing relationship on the signal pins. Each vendor of a microprocessor may have its own particular pattern for entering JTAG mode, and the number and types of settings that may be altered may also vary. The microprocessor has a plurality of JTAG registers. The particular values written into these registers determines the changes to the operating parameters of the microprocessor.
One particular setting that may be changed in the JTAG mode is the STPC settings for the various macros. One type of test that may be performed by changing the STPC settings is a margin test. The STPC settings are varied about the zero setting to determine if the device still operates correctly and efficiently at the rated clock frequency. It was noticed that some microprocessors that passed tests at the default zero STPC settings had stability problems after being run in an actual system environment. STPC margin tests revealed that, even though the devices with the higher failure rates passed the zero STPC test, their stability was compromised when the STPC settings were varied. The operating characteristics of any integrated circuit vary over time and based on the operating environment (e.g., temperature, humidity, etc.) Presumably, changes to the operating characteristics, albeit slight, could alter the operation of the device such that the timing relationships defined by the default STPC settings were not sufficient to avoid race conditions.
Due to the large number of macros in some integrated circuit devices, it is difficult to determine which of the individual macros have the potential for adversely affecting the operation of the device due to timing instabilities. Hence, it is difficult to direct the efforts of design engineers to optimize the timing of the devices and improve those macros that are susceptible to timing instabilities.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.